According to typical semiconductor device manufacturing techniques, semiconductor devices are formed in arrays as a plurality of integral regions of comparatively large semiconductor wafers. After the devices have been formed by a sequence of selective processing steps the wafers are separated along predetermined parting lines into the individual devices which are also referred to as chips.
A well known, rather basic electrical device is a diode. A well-known method of forming diodes from semiconductor wafers is to start with wafers of n-type semiconductor material. One of the major surfaces of each wafer becomes its back side which typically carries a metal deposit of uniform thickness. After separation of the wafer into individual devices, the metal deposit forms the back contact on the respective devices. The front side of each wafer is passivated such as by a formed oxide layer. By a series of typical selective treatment steps a plurality of separate p-type regions are formed in the wafer adjacent to the front side of the wafer. Each junction of the p-type region with the n-type wafer forms a separate diode. A window is then opened above each p-type region, the surface is metallized with a conductive film, and a metal contact, typically of silver, is electroplated in the window to a thickness that the contact extends at least to some height above the adjacent passivating layer on the surface of the wafer. After the contacts have been formed, the devices are complete, and the wafer is then separated into the individual diode chips.
In packaging the diode chips into typical axially-leaded diode circuit components, each of the chips is sandwiched between two flat ends of outwardly extending lead studs. The sandwiched assemblage is retained by a glass sleeve which becomes heat sealed about the two studs to retain the assemblage as a permanently assembled diode circuit component.
Problems with making diodes in the above-described manner are related to electroplating the contacts on the front side of the wafers. In general, the p-type regions adjacent to which the contacts are formed lend themselves to electroplating in that the plating current passes through the formed diode regions in the non-blocking direction. However, metal deposits are also formed at defect points in the passivating layer of the wafer outside of the p-type regions and particularly at the unprotected edges of the wafers. Since the applied plating current does not have to pass through the diode junction in its electrolytic path through any defects and consequently does not see the typical drop in voltage in the forward direction of the diode, metal deposits more quickly at the unwanted defect contact areas than at the actual contact areas.
Known plating techniques consequently use alternating plating currents whereby the wafer is subjected to a sequence of cycles of alternatingly plating currents and deplating currents. Consequently, all exposed areas in the first part of the cycle tend to become plated. However, in the second part of the cycle only the plated defects become deplated, since the deplating current is blocked by the diodes from passing through the desired diode contacts. Thus, a mechanism exists for minimizing the plating of shorting defects.
However, a problem of plating diode contacts at an economical rate and to an acceptable thickness is not overcome by such alternating current electroplating method. Problems in controlling the plating rate of alternating current plating methods have continued to exist. The reverse plating current tends to alter the plating conditions to prevent the diode contacts from being formed consistently to a predetermined contact height even though a given set of plating parameters has apparently not changed. Invariably occurring deviations from a desired plating cycle result in defective product, in loss of yield and in raised costs because of such losses and because of added downtime to restore the plating process to yield desired results.